1. Field
This invention relates to a nonvolatile semiconductor memory device.
2. Description of the Related Art
In NAND cell type flash memory, due to progress in the likes of shrinking of memory cells and multi-value technology for storing multiple data in a single memory cell, a voltage value of a lower limit of a threshold voltage distribution after execution of a data erase operation is attaining an increasingly low value (negative value of large absolute value). In the case of memory cells in an erase state having such a threshold voltage distribution of low voltage value, even if a write operation of data is performed on the memory cell, the threshold voltage distribution after write sometimes does not reach a positive value but remains a negative value.
Thus, the idea of setting to a negative value the voltage applied to the control gate of a selected memory cell during a read operation is also being studied. However, preparing a voltage of negative value as a voltage to be applied to the control gate requires a special voltage generating circuit, which leads to an increase in circuit area and an increase in power consumption.
Then, a NAND cell type flash memory system applies a positive voltage to a source line and a well (semiconductor layer where memory cells are formed), thereby no need to set to a negative voltage a read voltage applied to the control gate of a selected memory cell (below, such a system is referred to as a “negative sense scheme”). This negative sense scheme does not need a voltage generating circuit for generating a negative voltage for the control gate (word line) and enables increase in circuit area to be suppressed.